Projects
Jan 07-Present: Commodity-off-the-shelf based Reconfigurable 10Gbps Data Processing Platform
Nov 06-Present: Hardware Architecture for Bioinformatics Parsing Accelerator
Scalable Softcore Vector Processor for Biosequence Applications (FCCM06)
Jan 06-Present: Dynamic Thermal Management in Reconfigurable Hardware
An Adaptive Frequency Control Method using Thermal Feedback for Reconfigurable Hardware Applications (FPT06)
Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads (VLSI07)
Changing Output Quality for Thermal Management (FCCM07)
Adaptive Thermoregulation for Applications on Reconfigurable Devices (FPL07)
A Thermal Management and Profiling Method for Reconfigurable Hardware Applications (FPL06)
Jul 05-Nov 06: High-performance Streaming Data Clustering and Classification System
Streaming Hierarchical Clustering for Text Mining (AERO07)
Sensitivity Analysis of Gigabit Concept Mining System (AERO07)
Hardware-Accelerated Parser for Extraction of Metadata In Semantic Network Content (AERO07)
Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads (VLSI07)
High Speed Document Clustering in Reconfigurable Hardware (FPL06)
Jun 04-Nov 06: High-performance Network Packet Parser
Hardware-Accelerated Parser for Extraction of Metadata In Semantic Network Content (AERO07)
Content-Free Grammar Parsing for High-Speed Network Applications in Reconfigurable Hardware (DAC06)
A Reconfigurable Architecture for Multi-gigabit-Speed Content-based Routing (HOTI06)
Implementation of Network Application Layer Parser for Multiple TCP/IP Flows in Reconfigurable Devices (FPL06)
A Scalable Hybrid Regular Expression Pattern Matcher (FCCM06)
A Hardware Implementation of Hierarchical Clustering (FCCM06)
Reconfigurable Context-Free Grammar based Data Processing Hardware with Error Recovery (RAW06)
Context-Free Grammar based Token Tagger in Reconfigurable Devices (FPGA06)
LL(1) and *LR(1) for multiple thread(ANCHOR05)
Aug 01-Jun 04: High-performance Deep Packet Inspection
VLSI Architecture for Deep Packet Inspection (TVLSI)
Reconfigurable Architecture for Deep Packet Inspection (TECS)
ASIC Pattern Matching Co-processor for NIDS (DAC05)
Fast Reconfiguring DPI System for NIDS (FCCM04)
Scalable Reconfigurable DPI System (FPL02)
Aug 99-May 01: Beamformer using Quad G4 with AltiVec
M.S.E.E. Report Real-time beamformer
(
Slides
)
Aug 00: Foveated Video
Foveated Video
Apr 99: Myrinet on Fiber
Myrinet M2X-SC Converter
May 98: Two-Level Multicomputer
Two-Level Multicomputer
LANai 5 Baseboard ATR
Automatic Target Recognition
(
Slides
)
FPGA node test pack
LANai 4.X/5.X testboard
All purpose chip testboard DARPA project
Sep 97: Myrinet Switch M2M Oct Switch
Product Information
(
Photo
)
White Paper
Jul 97: CSPI Dual SAN2LAN
Product Information
May 96: Hand Shape Recognition
HSR Final Report
(
Slides
)
HSR Source Code
May 96: Very Long Instruction Word
VLIW Project Report
Dec 95: Artificial Kangaroo Leg
Kangaroo Leg (
Slides
,
Photo
,
Movie 1
,
Movie 2
)
Dec 95: Accomodative Glasses
Accomodative Project Report
(
Slides
,
Photo
,
Movie
)
Dec 94: Single Chip Multiprocessor
SCM Final Project Report
(
Photo
,
Appendices
)
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